Variable gain amplifiers for communication systems

ABSTRACT

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

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BACKGROUND OF THE INVENTION

The present invention is directed to electrical circuits and techniquesthereof.

A variable gain amplifier (VGA) has many applications. Typically,variable-gain or voltage-controlled amplifier is an electronic amplifierthat varies its gain depending on a control voltage (CV)/digital controlword. VGAs have many applications, including audio level compression,synthesizers, amplitude modulation, and others. For example, a VGA canbe implemented by first creating a voltage-controlled resistor (VCR),which is used to set the amplifier gain. The VCR can be produced by oneor more transistors with simple biasing. In certain implementation, VGAare implemented using operational trans-conductance amplifiers (OTA).Sometimes, VGAs are implemented for automatic gain control (AGC)applications. Typically, VGA performance can be measured in terms ofgain range, linearity of electrical characteristics, distortion,tunabiltiy, and bandwidth.

Over the past, many types of conventional variable gain amplifiers havebeen proposed and implemented in different applications. Unfortunately,existing variable gain amplifiers are inadequate, as explained below. Itis thus desirable to have new and improved variable gain amplifiers.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to electrical circuits and techniquesthereof. In various embodiments, the present invention provides avariable gain amplifier architecture that includes a continuous-timelinear equalizer (CTLE) section and a variable gain amplifier (VGA)section. The CTLE section provides both a pair of equalized data signalsand a common mode voltage. A DAC generates a control signal based on acontrol code. The VGA section amplifies the pair of equalized datasignals by an amplification factor using a transistor whose resistancevalue is based on both the common mode voltage and the control signal.There are other embodiments as well.

According to an embodiment, the present invention provides avariable-gain amplifier device, which includes an equalizer section thathas a first transistor and a second transistor. The first transistor hasa first gate terminal coupled to a first input signal and a first drainterminal coupled to a first output node. The second transistor has asecond gate terminal coupled to a second input signal and a second drainterminal coupled to a second output node. The equalizer section alsoincludes a first common mode resistor coupled to the first output nodeand a second common mode resistor that is coupled to the second outputnode and the first common mode resistor. The device includes adigital-to-analog (DAC) configured to generate a control voltage based again control code. The device also includes an amplifier section thathas a third transistor coupled and a fourth transistor. The thirdtransistor has a gate terminal coupled to the first output node and athird drain node coupled to a third output node. The fourth transistorhas a fourth gate terminal coupled to the second output node and afourth drain terminal coupled to a third output node. The amplifiersection also includes a fifth transistor that has a fifth gate terminalcoupled to the control voltage and common node between the first commonmode resistor and the second common resistor. The fifth transistor ischaracterized by a resistance value configured between source terminalsof the third transistor and the fourth transistor. The resistance valueis adjustable using the control voltage applied at the gate terminal.

According to another embodiment, the present invention provides avariable gain amplifier device that has a first transistor and a secondtransistor. The first transistor has a first gate terminal coupled to afirst input signal and a first drain terminal coupled to a first outputnode. The second transistor has a second gate terminal coupled to asecond input signal and a second drain terminal coupled to a secondoutput node. The device also includes a first common mode resistorcoupled to the first output node. The device further includes a secondcommon mode resistor coupled to the second output node and the firstcommon mode resistor. The device additionally includes a first loadresistor coupled to the first output node. The device also includes adigital-to-analog (DAC) configured to generate a control voltage based again control code. The device further includes a third transistorcoupled and a fourth transistor. The third transistor has a third gateterminal coupled to the first output node and a third drain node coupledto a third output node. The fourth transistor includes a fourth gateterminal coupled to the second output node and a fourth drain terminalcoupled to a third output node. The device further includes a fifthtransistor comprising a fifth gate terminal coupled to the controlvoltage and common node between the first common mode resistor and thesecond common resistor. The fifth transistor is configured to operate ina triode region and characterized by a resistance value configuredbetween source terminals of the third transistor and the fourthtransistor. The resistance value is adjustable using the controlvoltage.

According to yet another embodiment, the present invention provides aSerDes apparatus that has a data communication interface for receiving adifferential input signal with required common mode voltage. Theapparatus also includes a loss of signal detection module configured forchecking signal presence at the data communication interface. Theapparatus also includes a CTLE section configured for providing a commonmode voltage and a first equalized signal and a second equalized signalbased at least on the first input signal and the second input signal.The apparatus also includes a DAC section configured for generating acontrol signal based on a control code. The apparatus also includes aVGA section that has a transistor and configured to generate a firstamplified signal and a second amplified signal based on the firstequalized signal and the second equalized signal. A gain ratio betweenthe first amplified signal and the first equalized signaled is dependson the VGA load and degeneration resistance. The degeneration resistancevalue is a function of the common mode voltage and the control signal.The apparatus also includes a clock data recovery module beingconfigured to generate a clock signal using at least the first equalizesignal and the second equalized signal.

It is to be appreciated that embodiments of the present inventionprovide many advantages over conventional techniques. Compared toconventional techniques, VGA architecture according to embodiments ofthe present invention can provide a high level of SNR and tunability,and at the same time low parasitic capacitance at critical nodes.

Embodiments of the present invention can be implemented in conjunctionwith existing systems and processes. For example, existing communicationdevices such as SerDes can readily incorporate embodiments of thepresent invention. VGA architectures according to embodiments of thepresent invention can take advantage of front end CTLE configurationsthat are already parts of communication devices. Embodiments of thepresent invention are compatible with existing manufacturing processesand equipment. There are other benefits as well.

The present invention achieves these benefits and others in the contextof known technology. However, a further understanding of the nature andadvantages of the present invention may be realized by reference to thelatter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following diagrams are merely examples, which should not undulylimit the scope of the claims herein. One of ordinary skill in the artwould recognize many other variations, modifications, and alternatives.It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this process andscope of the appended claims.

FIG. 1 is a simplified block diagram illustrating a communication systemaccording to embodiments of the present invention.

FIG. 2A is a simplified diagram illustrating a conventional VGA.

FIG. 2B is a simplified diagram illustrating a triode region transistorthat can be used to implement a variable resistor.

FIG. 2C is a diagram illustrating a conventional VGA.

FIG. 3 is a simplified diagram illustrating a VGA according toembodiments of the present invention.

FIG. 4 is a simplified diagram illustrating operation of VGAarchitecture 300 according to embodiments of the present invention.

FIG. 5 is a graph illustrating VGA gain in relation to the DAC gaincontrol code according to embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to electrical circuits and techniquesthereof. In various embodiments, the present invention provides avariable gain amplifier architecture that includes a continuous-timelinear equalizer (CTLE) section and a variable gain amplifier (VGA)section. The CTLE section provides both a pair of equalized data signalsand a common mode voltage. A DAC generates a control signal based on acontrol code. The VGA section amplifies the pair of equalized datasignals by an amplification factor using a transistor whose resistancevalue is based on both the common mode voltage and the control signal.There are other embodiments as well.

As explained above, variable gain amplifiers (VGA) have a wide range ofapplications. For example, VGAs are often used in communicationapplications. For example, as a part of a serializer/deserializer(SerDes) system, a VGA can be used to amplify amplitude of receivedanalog signal before other processing techniques (e.g., clock recovery,ADC conversion, etc.) are performed. Depending on actual application andimplementation of VGAs, there are various desirable VGA characteristics,such as low noise, small parasitic capacitance on the output nodes, andhigh linearity.

It is to be appreciated that according to various embodiments of thepresent invention, VGAs are implemented in conjunction with continuoustime linear equalizers. Continuous time linear equalizers are typicallyincluded in various types of communication and data processing systems.For example, a SerDes system includes both a transmitter module and areceiver module. Received analog signals, transmitted as a differentialpair, are first processed by a continuous-time linear equalizer (CTLE)and then amplified by a VGA. In various embodiments of the presentationinvention, VGAs are implemented in conjunction with CTLE. Additionally,one or more digital-to-analog converters (DAC) are used to providecontrol signal for both the CTLE and the VGA.

FIG. 1 is a simplified block diagram illustrating a communication systemaccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. In FIG. 1, the transmitter(TX) transits data signal, as a differential signal, to the receiver(RX) via a pair of communication channels. For example, thecommunication channels can be existing copper wires. At the receiver,the input signals are received at the input terminals with inductorcoils and input resistors that improve signal quality. The CTLE moduleis implemented as a part of the receiver. Input signals are equalized bythe CTLE before further processing. For example, loss of signaldetection (LOSD) module determines whether there is signal beingreceived. Once it is determined that there are signal coming from thetransmitting entity (TX), equalization is performed by the CTLE module.On the other hand, if the LOSD module fails to detect signal presence(or detecting a lack of signal presence), signal processing is notperformed. For example, the CTLE module is used as a component of ananalog front end portion of the communication device. The equalizedsignal, which is a differential pair, is then provided to the VGA asshow. The VGA is specifically configured to amplify the received signalby a predetermined amount, and the VGA operates in conjunction withCLTE. For example, compared to conventional VGAs implemented withswitchable resistor array, VGA implementations according to embodimentsof the present invention offer improved performance by taking advantageof the CTLEs. It is to be appreciated that the use of CTLEs with VGAstakes advantage of the fact that CTLEs are essential front end circuitof the receiver devices. For example, receivers are generallyimplemented with CTLEs followed by one or more VGAs. For example, theVGA is configured to enable constant output voltage swing at the outputfor a different set of channel lengths by adjusting the gain controlcode. It is to be appreciated that VGAs according to embodiment of thepresent invention help maintain linearity. The available signal swing atthe output stage can be adjusted using VGAs. For ADC based communicationlinks, automatic gain control often allows for reduced resolution andfull-scale range requirement of the ADCs. As mentioned above, VGAsaccording to the present invention provide high SNR, fine tunability(e.g., 5 to 8 bits), and small parasitic capacitance at the criticalnodes.

As shown in FIG. 1, after equalization is performed by the CTLE moduleand adjusted by the VGA, signal processing such as clock data recovery(CDR), analog to digital conversion (ADC), and/or other processes arethen performed. It is to be appreciated that the receiver illustrated inFIG. 1 can be used in a variety of applications and systems. Forexample, the receiver can be a part of a transceiver device. In variousembodiments, receivers are implemented as parts of SerDes system.

As mentioned above, conventional VGAs are often implemented with aswitchable resistor array. FIG. 2A is a simplified diagram illustratinga conventional VGA. A conventional VGA includes a pair of inputtransistors for receiving differential input signals. As shown, inputINP is coupled to the gate terminal of transistor M_(1A), and input INNis coupled to the gate terminal of transistor M_(1B). A switchableresistor array section is coupled to the source terminals of transistorsM_(1A) and M_(1B). Outputs at the drain terminals of transistors M_(1A)and M_(1B) are coupled to load resistors R_(L) and load capacitor C_(L).Supply voltage is provided at terminal V_(dd). Tail current source isprovided through transistors M_(T).

To change the output gain, control signal is applied to the switchtransistors M_(SW). Ideally, output gain is linearly proportional to theamplitude of control signal within a large operating frequency range.Unfortunately, the performance of conventional VGA architectureillustrated in FIG. 1 is far from ideal. Among other things, capacitanceat node X and Y would limit the frequency response. Additional, thiscapacitance may cause undesirable phase shift and group delay describedbe Equation 1 below:

$\begin{matrix}{{{Frequency}\mspace{14mu}{dependent}\mspace{14mu}{amplifier}\mspace{14mu}{gain}} = {\frac{g_{m\; 1}}{1 + \frac{g_{m\; 1}R_{\deg}}{2 + {{SC}_{P}R_{\deg}}}}\frac{R_{L}}{1 + {{SC}_{L}R_{L}}}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

Depending on the implementation, the parasitic capacitance can increasewith number of gain steps and gain range (i.e., depending on the numberof switches). More specifically, when increasing number of gain steps,number of switches increases accordingly (e.g., 32 for 5-bits gaincontrol). The increased number of switches introduces a lot ofundesirable coupling capacitance in the signal path in the circuitphysical layout. The coupling capacitance usually leads to impairedfrequency response for the VGA.

In addition to switch resistor array configuration illustrated in FIG.2A, conventional systems also provide for variable resistorimplementation. For example, the switch resistors array illustrated inFIG. 2A can be replaced by one or more variable resistors. FIG. 2B is asimplified diagram illustrating a triode region transistor that can beused to implement a variable resistor. For example, the drain-to-sourceresistance of the triode region transistor changes continuously withgate voltage change. Even for a wide range of gain variations, a singletransistor may be sufficient, thus eliminating the need for havingmultiple resistors and switches. The reduced number of resistiveelements can effectively reduce the undesirable parasitic capacitanceassociated with switches. For example, the resistance value of thetriode region transistor in FIG. 2B can be described by Equation 2below:

$\begin{matrix}{R_{ds} = \frac{1}{u_{n}C_{ox}\frac{W}{L}\left( {V_{gs} - V_{th}} \right)}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

For example, the resistance value R_(ds) can be adjusted by changing thevoltage applied to the gate of the triode region transistor. A gaincontrol module is coupled to the triode region transistor and appliesthe gate voltage accordingly. Unfortunately, the use of triode regiontransistors in lieu of resistor arrays has its own drawbacks. The gaincontrol transistor needs to operate in triode region during the entiresignal swing. Otherwise, the triode region transistor would behave as acurrent source as opposed to the intended resistor which limits gain andlinearity.

FIG. 2C is a diagram illustrating a conventional VGA. Triode regiontransistor M_(GC) operates as a variable gain resistor, and itsresistance value is based its gate voltage at point Z. The gate voltageis provided by a DAC, which coverts gain control code to the gatevoltage. As mentioned above, transistor M_(GC) needs to operate intriode region for the VGA to work, and that means the gate voltage atnode Z need to be higher than voltage at node X, and the voltagedifference should be great than the transistor threshold voltage V_(th).Triode region voltage can be expressed by Equation 3 below:V _(Z) >V _(X) +V _(th)  Equation 3

To maintain voltage V_(Z), the DAC output voltage needs to bemaintained. For example, the DAC gain control code can be preprogrammedto avoid voltage V_(Z) dropping too low. A major drawback for VGA inFIG. 2C is thus the dependence on the DAC output. For example,deviations from the DAC output could cause transistor M_(GC) to enternon-triode mode and result in VGA non-linearity. It is to be appreciatedthat embodiments of the present invention implement efficient VGAstructures with few of the conventional VGA drawbacks.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

As mentioned above, VGAs according to embodiments of the presentinvention are implemented in conjunction with CTLEs. FIG. 3 is asimplified diagram illustrating a VGA according to embodiments of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. Asshown, the VGA architecture 300 includes a CTLE section 310 and a VGAsection 320. For example, CTLE section 310 and VGA section 320 are bothparts of a large device, such as a receiver or a SerDes front end. Amongother things, CTLE section 310 provides equalized differential signalsthat is to be amplified by the VGA section 320. CTLE section 310additionally provides control signal for transistor M_(GC), whichfunctions as a voltage controlled variable resistor. By injectingcontrolled amount of current into the CTLE section 310, VGA architectureensures the adequate gate voltage for transistor M_(GC) which issufficiently above the threshold voltage keep transistor M_(GC)operating in its triode region.

As shown in FIG. 3, input signals are received by the input transistorsat the CTLE section 310. Positive input signal “INP” is provided at thegate of transistor M_(1C), and the negative input signal “INN” isprovided at the gate of transistor M_(1D). The source terminals oftransistors M_(1C) and M_(1D) are coupled to current sources. CTLEoutput signals V_(op1) and V_(on1) of the CTLE are provided at the drainterminals of transistors M_(1C) and M_(ID). The drain terminals oftransistors M_(1C) and M_(1D) are additionally coupled to load resistors311 and 312. A pair of common mode resistors 313 and 314 are providedbetween the two output signals to sense the common mode voltage. CTLEoutput signals V_(op1) and V_(on1) are provided to the input transistorsof VGA section 320. Supply voltage for both CTLE section 310 and VGAsection 320 is provided at terminal V_(dd) as shown.

The amplification of the VGA architecture, which determines swingmagnitude of output signals V_(op2) and V_(on2), is based on theresistance value (between point X and point Y) of transistor M_(GC). Tochange the resistance value of transistor M_(GC), the control voltageapplied to the gate of transistor M_(GC) (or node Z) is adjusted. Thecontrol voltage at node Z is a function of both output of DAC 301 andcommon node voltage between resistors 313 and 314. The common nodevoltage between resistors 313 and 314 ensures that a minimum voltagelevel is provided, as the voltage of control signal provided by DAC 301is added on top of the common voltage at node W.

Output signals V_(op1) and V_(on1) of CTEL section 310 are equalizedsignals used as input signals for VGA section 320. As an example, VGAsection 320 is implemented with both differential inputs anddifferential outputs. Differential inputs are provided at gate terminalsof transistors M_(1A) and M_(1B). For example, transistors M_(1A) andM_(1B) are implemented using PMOS devices, but it is to be appreciatedthat other types of transistor devices are possible as well. TransistorsM_(1A) and M_(1B) amplify V_(op1) and V_(on1) received at theirrespective gate terminals. The amount of amplification largely dependson the resistance between node X and node Y. For example, transistorM_(GC) is a triode region biased in transistor, and it operates as aresister as long as the voltage at node Z is above the threshold voltageV_(th) of transistor M_(GC). The common mode node W, as explained above,can be configured to have a voltage level that is always higher than thethreshold voltage of transistor MGC. In various embodiments, common moderesistors 313 and 314 are specifically configured to have a much higherresistance value than the load resistors 311 and 312. In variousembodiments, at CTLE section 310 the common mode resistor value is atleast ten times greater than the load resistor value to avoid loading onthe CTLE due to the invention. For example, the resistance of commonresistor 314 is around 10KΩ, while the resistance of load resistor 312is about 150Ω.

In various embodiments, the control voltage from DAC 301 is specificallycalibrated relative to the common mode voltage at node W. Digitalcontrol codes used as input for DAC 301 are calibrated according tocommon mode voltage at node W and the threshold voltage of the triodetransistor M_(GC). It is to be understood while the threshold voltage ofthe triode transistor M_(GC) is device specific and stays constant forthe device, common mode voltage at node W may change due to differentsupply voltage at V_(dd) or voltage of input signals. In certainimplementations, a control module (not shown in FIG. 3) determines whatgain control code to be fed into DAC 301 based on the supply voltageV_(dd) and voltage swing of input signals INP and INN.

Depending on the implementation, the gain control code for the DAC 301can be set in various ways. For example, a feedback mechanism may beused to determine the common mode voltage at node W, and a controlgenerates gain control accordingly. In various embodiments, swing ofinput voltage is predetermined to be within a range, and the gaincontrol code is calibrated accordingly. For example, the gain controlcode may be stored at a lookup table.

At the VGA section 320, output signals are provided at V_(op2) andV_(on2), where the signals received from the CTLE section 310 areamplified by a factor based on the resistance value of transistorM_(GC). At the VGA section 320, output nodes V_(op2) and V_(on2) arealso coupled to load resistors and load capacitors. For example, V_(op2)is coupled to load resistor 321 and load capacitor 323; V_(on2) iscoupled to load resistor 322 and load capacitor 324. In variousimplementations, use and arrangement of load resistors and capacitorsmay be modified.

FIG. 4 is a simplified diagram illustrating operation of VGAarchitecture 300 according to embodiments of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. The voltages of the nodesX, Y, and Z of VGA architecture 300 are shown. For the purpose ofillustration, a 10 GHz sine wave differential signal is used as theinput signal. The common mode voltage is about 500 mV, which is appliedto node Z. The swing voltages of the output signals V_(op1) and V_(on1)around the common mode voltage of about 500 mV. In comparison, signalsat nodes X and Y swing around 290 mV. This translates to at least 200 mVV_(gs), the voltage differential between gate voltage and thesource/drain voltage, for the transistor M_(GC). The output of the DAC301 is added to the 200 mV V_(gs), and the 200 mV functions as a bufferthat prevents transistor M_(GC) from moving out of its triode region. Itis to be appreciated that while the DAC output voltage may change duringoperation, the common node voltage at the CTLE section 310 provides abuffer voltage that keeps transistor M_(GC) in its triode region.

FIG. 5 is a graph illustrating VGA gain in relation to the DAC gaincontrol code according to embodiments of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, a 6-bits gaincontrol code is used for DAC 301 in FIG. 3. The 6-bits of gain controlcode translates to 64 steps (2⁶), as shown in the horizontal axis. TheVGA gain for VGA architecture 300 is adjusted from about −2.5 dB toabout 6.5 dB. It is to be appreciated that the relationship between theVGA gain and the DAC code is substantially linear over the entire range,and there is no spikes caused by triode region transistors moving in andout of its triode region.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A variable-gain amplifier device comprising: anequalizer section comprising: a first transistor and a secondtransistor, the first transistor comprising a first gate terminalcoupled to a first input signal and a first drain terminal coupled to afirst output node, the second transistor comprising a second gateterminal coupled to a second input signal and a second drain terminalcoupled to a second output node; a first common mode resistor coupled tothe first output node; a second common mode resistor coupled to thesecond output node and the first common mode resistor; adigital-to-analog (DAC) configured to generate a control voltage based again control code; an amplifier section comprising: a third transistorand a fourth transistor, the third transistor comprising a third gateterminal coupled to the first output node and a third drain node coupledto a third output node, the fourth transistor comprising a fourth gateterminal coupled to the second output node and a fourth drain terminalcoupled to a third output node; and a fifth transistor comprising afifth gate terminal coupled to the control voltage and common nodebetween the first common mode resistor and the second common resistor,the fifth transistor being characterized by a resistance valueconfigured between source terminals of the third transistor and thefourth transistor, the resistance value being adjustable using thecontrol voltage.
 2. The device of claim 1 further comprising: a firstload resistor coupled to the first output node; a second load resistorcoupled to the second output node.
 3. The device of claim 2 furthercomprising a current source coupled to a source terminal of the firstinput transistor.
 4. The device of claim 2 further comprising a voltagesupply coupled to the first resistor.
 5. The device of claim 1 furthercomprising: a first load capacitor coupled to the third output node; asecond load capacitor coupled to the fourth output node.
 6. The deviceof claim 1 wherein a sum of a common voltage and the control voltage isgreater than a threshold voltage of the fifth transistor.
 7. The deviceof claim 6 wherein the fifth transistor comprises a triode regiontransistor.
 8. The device of claim 6 wherein the threshold voltage isassociated with a gate-source voltage differential.
 9. The device ofclaim 1 wherein the gain control code is calibrated based at least on avoltage of the common node.
 10. The device of claim 9 wherein resistancevalue is substantially linear relative to the gain control code.
 11. Avariable gain amplifier device comprising: a first transistor and asecond transistor, the first transistor comprising a first gate terminalcoupled to a first input signal and a first drain terminal coupled to afirst output node, the second transistor comprising a second gateterminal coupled to a second input signal and a second drain terminalcoupled to a second output node; a first common mode resistor coupled tothe first output node; a second common mode resistor coupled to thesecond output node and the first common mode resistor; a first loadresistor coupled to the first output node; a digital-to-analog (DAC)configured to generate a control voltage based a gain control code; athird transistor and a fourth transistor, the third transistorcomprising a third gate terminal coupled to the first output node and athird drain node coupled to a third output node, the fourth transistorcomprising a fourth gate terminal coupled to the second output node anda fourth drain terminal coupled to a third output node; and a fifthtransistor comprising a fifth gate terminal coupled to the controlvoltage and common node between the first common mode resistor and thesecond common resistor, the fifth transistor being configured to operatein a triode region and characterized by a resistance value configuredbetween source terminals of the third transistor and the fourthtransistor, the resistance value being adjustable using the controlvoltage.
 12. The device of claim 11 wherein the first transistorcomprises a PMOS transistor.
 13. The device of claim 11 wherein thethird transistor comprises a PMOS transistor.
 14. The device of claim 11further comprising a voltage supply coupled to the first load resistor.15. The device of claim 11 wherein the control voltage is predeterminedbased on a common mode voltage and a triode region voltage associatedwith the fifth transistor.
 16. A serializer/deserializer (SerDes)apparatus comprising: a data communication interface for receiving afirst input signal and a second input signal; a loss of signal detectionmodule configured for checking signal presence at the data communicationinterface; a continuous-time linear equalizer (CTLE) section configuredfor providing a common mode voltage and a first equalized signal and asecond equalized signal based at least on the first input signal and thesecond input signal; a digital-to-analog (DAC) section configured forgenerating a control signal based on a control code; a variable gainamplifier (VGA) section comprising a transistor and configured togenerate a first amplified signal and a second amplified signal based onthe first equalized signal and the second equalized signal, the VGAsection being characterized by a gain ratio being based on a ratiobetween a load resistance and a degeneration resistance value of thetransistor, the degeneration resistance value being a function of thecommon mode voltage and the control signal; and a clock data recoverymodule being configured to generate a clock signal using at least thefirst equalize signal and the second equalized signal.
 17. The apparatusof claim 16 wherein the clock data recovery module operates in a standbymode if the loss of signal detection module fails to detect signalpresence.
 18. The apparatus of claim 16 wherein the data communicationinterface is coupled to a wired communication lane.
 19. The apparatus ofclaim 16 wherein data communication interface is coupled to one or moreinput inductors.
 20. The apparatus of claim 16 wherein the datacommunication interface is coupled to one or more input resistors.